1. Field of the Invention
The present invention relates to a power semiconductor device which is an integrated circuit (IC) incorporating a power semiconductor element having a gate, that is insulated from the semiconductor substrate by a thin oxide film layer, and a voltage applying circuit for applying a predetermined voltage to the gate of the power semiconductor element.
2. Related Art
Generally known as power semiconductor device having a thin oxide layer insulating a gate from the semiconductor substrate is, for example, a power MOSFET (i.e., metal oxide semiconductor field-effect transistor). From the necessity of forming the gate oxide film very thin in such a MOSFET, the manufacturing of the same usually encounters with thickness dispersion in the formation of this thin oxide film, the degree of which generally approximates the thickness of a wafer.
The thickness dispersion of thin oxide film is directly related to the withstand voltage at the gate of the power MOSFET when completely manufactured as a product.
To prevent possible initial defects, particularly those occurring when a predetermined voltage is applied to the MOSFET gate, gate withstand voltage tests are normally conducted in a wafer condition or a product-assembled condition before finishing manufacturing of a product. This assures the ability of the gate to withstand a voltage within a pre-designated range. The level of gate withstand voltage to be assured, in this case, is set higher than the normally applied gate voltage in operation This helps to compensate for a decline in the gate's withstanding ability due to deterioration in quality of its oxide film layer. Similarly, to test reliability of the gate withstand voltage, a gate voltage that may be higher than that in the normal operation is applied.
On the other hand, the gate oxide film of the power MOSFET, which is very thin as described above, may be damaged when exposed to a voltage exceeding the gate withstand voltage. Such a voltage may result from static electricity or excessive voltage generated in the handing or operating condition. To prevent such an accidental damage, one of prior art technologies teaches interposing a Zener diode between the gate terminal and the source terminal of the power semiconductor element beforehand. According to this conventional technology, Zener voltage of the Zener diode is set lower than the gate withstand voltage. This arrangement prevents the gate oxide film from being damaged when an excessive voltage is applied to the gate, because the Zener diode is broken down first so as to absorb the excessive voltage applied.
However, above-described break-down of Zener diode is disadvantageous in that, when a higher gate voltage is intentionally applied to a power MOSFET in the gate withstand voltage test, a voltage actually applied to the gate is limited within the Zener voltage of the Zener diode which is smaller than that of the required gate voltage for the withstand voltage test, thus resulting in impossibility or failure of test.
Unexamined Japanese Patent Application No. HEI 2-288366/1990 solves such problems by independently providing a gate terminal for test use only as shown in an equivalent circuit of FIG. 7. A gate terminal G, serving as an external terminal, is connected to a gate of a power MOSFET 1 through serial resistances 2 and 3. A gate testing terminal C is connected to the gate of the power MOSFET 1 through a resistance 4. A gate protecting Zener diode 5 is interposed between a common connecting point joining the resistances 2, 3 and a source S of the power MOSFET 1. A test-use Zener diode 6 is interposed between the gate and the source of the power MOSFET 1. Zener voltages VZ1 and VZ2 of these Zener diodes 5 and 6 -- for example, VZ1=6V and VZ2=36V satisfy the relationship of VZ1&lt;VZ2.
In operation, the power MOSFET 1 is activated in an operating condition upon reception of a gate signal from the gate terminal G. If an excessive voltage is applied to the gate terminal G and exceeds the Zener voltage VZ1, the Zener diode 5 causes breakdown based on its Zener effect which results in absorption or elimination of the excessive voltage received. Thus, the gate of the power MOSFET 1 is not subjected to any excessive voltage at all.
In a gate withstand voltage test or an execution of gate screening, a testing voltage is applied to the gate testing terminal C. As the gate testing terminal C is connected through the resistance 3 to the Zener diode 5, the magnitude of a voltage applied to the gate testing terminal C can be increased up to the Zener voltage VZ2 of the testing Zener diode 6 which is larger than the Zener voltage VZ1 of the Zener diode 5. Thus, the gate screening of the power MOSFET 1 can be executed by applying a voltage higher than a normal operation voltage.
However, this circuit raises such a problem that switching speed is undesirably reduced due to existence of the resistance 3. More specifically, the gate of the power MOSFET 1 has a significant amount of capacitance which is likely to increase a time constant of charge/discharge when combined with a resistance such as the resistance 3. Hence, the reduction of switching speed reflects such an increase of time constant of charge/discharge.